The present invention relates to a method and an apparatus for controlling interruption of a processor, and more particularly to interruption in the course of instruction execution.
In order to speed up character processing or list processing, processing may be implemented by firmware. However, because an execution time for each instruction is very long, a response to an external input will be lowered unless an interruption is permitted in the course of instruction execution. Such interruption in the course of instruction execution is shown in VAX 11 Architecture Handbook and U.S. Pat. No. 3,401,375.
Pertinent portions of the prior art are briefly explained. As shown in FIGS. 2A and 2B, in a conventional interruption, when an interruption is requested, a program counter and a program level are switched at a break of an instruction, and the program counter and program level are restored after interruption processing. On the other hand, in a processor status longword described in the VAX 11 Architecture Handbook, pages 52 and 53, a first part done (FPD) flag is provided to carry out control as shown in FIGS. 3A and 3B to permit the interruption in the course of instruction execution.
In the method shown in FIGS. 3A and 3B, if repetitive processing is to be carried out by a work register, a content of the register at an interruption destination will be destroyed. Accordingly, the repetitive processing must be performed by a general purpose register. Thus, a plurality of general purpose registers are required for one instruction. Because the general purpose registers are used for other purpose, it is necessary to save contents of the registers which may be destroyed, prior to the execution of the instruction which includes the repetitive processing, and to restore those registeres after the completion of the instruction execution. This is wasteful processing. Further, the process must return to an address .circle.D in FIG. 3A by a restore instruction, and decision as to whether the FPD flag is "1" or not must be made.
An execution time of such an instruction is not always long but an execution time may be short for searching or pattern matching. Accordingly, a proportion occupied by saving and restoring is large. For example, where this instruction is used to transfer 16 bytes of data and 4 bytes of data are read or written by each memory access, four times of register saving access, eight times of memory access and four times of register restoring access are required. Thus, 50% of total access time is spent for the register saving and restoring accesses.